(1) Field of the Invention
The present invention relates to processes used to fabricate semiconductor devices, and more specifically to a semiconductor fabrication process which results in reliability improvements for specific devices, on a semiconductor chip, while maintaining the performance of other devices, fabricated on the same semiconductor chip.
(2) Description of the Prior Art
Most semiconductor chip designs request high voltage, input/output, (I/O), devices, along with core devices, which operate at lower voltages than the I/O device counterparts. To realize maximum performance, the core devices are created featuring short channel regions. The use of the performance enhancing short channel regions, for the core devices, require such features as heavier channel doping, anti-punchthrough implant regions, and shallow, abrupt source/drain regions, which would be adversely influenced by transient enhanced diffusion, (TED), which would disrupt, or alter, the intricate concentration profile of these features. Therefore a rapid thermal anneal, (RTA), procedure, is used to activate the ion implanted species, used to create features such as a lightly doped source/drain, (LDD), region, resulting in activation of the implanted species, however without diffusion, or movement of the implanted species, thus preserving the desired dopant concentration profile, and allowing the performance offered by these features, such as the LDD source/drain region, to be realized.
The I/O devices, however operating at a higher voltage than the core memory device counterparts, are more susceptible to a hot carrier effect, (HCE), when created using the sharper dopant profiles, used for the core devices. The I/O devices would benefit, in terms of a decreased HCE reliability phenomena, from graded dopant profiles, obtained via procedures presenting TED. This invention will describe a process in which I/O devices are fabricated, featuring graded, less abrupt dopant regions, enhancing reliability, while the core devices are simultaneously fabricated, with the sharper diffusion regions, needed for performance. This is accomplished via a process sequence which delays the creation of critical I/O dopant regions, to after the use of an RTA procedure, used to activate dopants in only the core device regions. After creation of the I/O LDD regions, subsequent thermal procedures, resulting in TED, will allow the desired grading of the I/O dopant regions to occur, while the RTA treated core device regions, will remain unmoved. Prior art, such as an article titled, "A Comprehensive Study of Performance and Reliability of P, As and Hybrid As/P n LDD Junctions for Deep-Submicron CMOS Logic Technology", by Nayak et al, in IEEE ELECTRON DEVICE LETTERS, Vol. 18, No. 6, June 1997, describes a method in which the LDD is fabricated using both arsenic and phosphorous, to enhance performance, and preserve reliability. That prior art however, does not show the process described in this invention, in which both I/O and core devices, are simultaneously created, each exhibiting the desired dopant profile, achieved via delaying the creation of the dopant regions of the I/O devices, to a point in the fabrication sequence, in which the core device, dopant regions, have already been fixed.